To address the growing computational demands, researchers from the Indian Institute of Technology (IIT) Guwahati have come up with a developed technology for designing fast, efficient, secure and dependable integrated circuits (ICs). A group of researchers from the institute has aimed to solve the problem of inefficiency of the multi-core processors, which are being presently used in computing.
Commenting on the research, Chandan Karfa, Associate Professor, Department of Computer Science and Engineering, IIT Guwahati, said, "It is a promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system. For example, visualisation processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks," reported PTI.
Hardware acceleration specifications are often written in high-level languages like in C and C++ and are converted to hardware code (or Register-Transfer Level) in a process called High-Level Synthesis (HLS). "Due to the complex conversation process, HLS translation may introduce bugs in the design and, therefore, stringent validation steps are required," the team has explained.
"We have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators. The other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification. There is no other tool in the market with similar features," the team stated, PTI reported.
"In addition to these simulators, prototypes of which are available for testing, the team has also developed a technology called HOST, which protects Integrated Circuits from IP theft during the design cycle. It has been shown to be resilient to any known attack till date," the team has added further.
